次态卡诺图在时序逻辑电路分析和设计中的运用  

On the Application of Hypo-state Karnaugh Map in the Analysis and Design of Time-Sequence Logic Circuit

作　　者：倪树范[1] 

机构地区：[1]绵阳师范高等专科学校物理系,绵阳621000

出　　处：《绵阳师范高等专科学校学报》2000年第5期30-37,共8页Journal of Mianyang Teachers College

摘　　要：通过实际例子 ,阐述了次态卡诺图在分析和设计时序逻辑电路中的使用方法。该方法的使用可以使时序逻辑电路的分析和设计得到一定的简化 ,过程中思路清晰 ,状态转换直观。Based on practical examples,this paper expounds the applied method hypo-state Karnaugh map in the analysis and design of time-sequence logic circuit;this method can simplify the analysis and design of time-sequence logic circuit,make its train of thought in the process clear and change its state directly.

关 键 词：次态卡诺图 时序逻辑电路 电路分析 电路设计 

分 类 号：TN791[电子电信—电路与系统] TN702