基于CPLD的数字移相分频钟  

A Digital Phase-Shifting Frequency-Dividing Clock Designed with CPLD

作　　者：杨蕾[1] 胡永辉[1] 翟慧生[1] 

机构地区：[1]中国科学院国家授时中心

出　　处：《时间频率学报》2004年第1期1-7,共7页Journal of Time and Frequency

摘　　要：设计了一种数字移相分频钟 ,其中利用了先进的复杂可编程逻辑器件(CPLD -ComplexProgrammableLogicDevice)技术 ,将硬件电路模块化 ,把各功能模块集成在一个芯片中。与以往用分立元件设计硬件电路相比 ,具有电路简单 ,可靠性高 。A digital phase-shifting frequency-dividing clock has been designed with CPLD(Complex Programmable Logic Device) technique which modularizes hardware circuit and integrates different modules into one chip.Compared with original circuit designed with separate components this design is characterized by simple hardware circuit and high reliability,and is easy to be debugged.

关 键 词：CPLD 数字移相分频钟 电路设计 工作原理 

分 类 号：TH714[机械工程—测试计量技术及仪器]