JPEG2000中算术编码器的FPGA实现  

FPGA Implementation of Arithmetic Encoder in JPEG2000

作　　者：李德建[1] 孟鸿鹰[1] 王志华[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《微电子学》2002年第4期245-248,252,共5页Microelectronics

摘　　要：研究了 JPEG2 0 0 0标准中算术编码器的硬件实现问题 ,提出了一种适合 VLSI实现的结构 ,并在 FPGA上对其进行了仿真验证。该设计使用 Verilog语言在 RTL级描述 ;并以 AlteraFLEX1 0 K1 0 0 - 3为基础 ,在 Maxplus II下完成综合及后仿真。综合得到的器件面积利用率 1 6 % ,最高工作时钟 3 1 .4MHz。分析表明 ,这种结构能够满足 JPEG2 0 0 0系统对 5 1 2× 5 1Hardware implementation of the arithmetic encoder in JPEG2000 standard is investigated in the paper An architecture suitable for VLSI implementation is presented, which is simulated and verified on FPGA The design is described at RT level using Verilog HDL Based on Altera FLEX10K100 3, synthesis and post simulation are conducted with Maxplus II 16% of the logic resource is used for the synthesized device and the estimated clock is 31 4 MHz Analysis indicates that the device can meet the requirement of JPEG2000 system for real time processing of a 512 × 512 grayscale image

关 键 词：算术编码器 FPGA JPEG2000 图像压缩 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]