有限冲激响应滤波器的设计与实现  

Design and Implementation of Finite Impulse Response (FIR) Filter

作　　者：阮颐[1] 黄培中[1] 卫炎[2] 

机构地区：[1]上海交通大学电子工程系,上海200030 [2]航天时代电子公司研究院上海分中心,上海200233

出　　处：《上海交通大学学报》2004年第12期2045-2047,共3页Journal of Shanghai Jiaotong University

摘　　要：提出了采用现场可编程门阵列(FPGA)器件实现有限冲激响应(FIR)数字滤波器的方案,并以一个8阶低通FIR数字滤波器的实现为例,设计并完成软硬件仿真与验证.结果表明,电路工作正确可靠,能满足设计要求.In the field of digital design system, field programmable gate array (FPGA) design is one of the most important methods for its feature of reconstruction and ISP. Using very-high-speed-integrated circuit hardware description language (VHDL) implentation for example, the article is mainly about the FPGA design of an eighth order FIR filter, which is verified in the digital signal process circuit of fiber optic gyro.

关 键 词：有限冲激响应滤波器 现场可编程门阵列 超高速集成电路 硬件描述语言 光纤陀螺 数字信号处理 

分 类 号：TN99[电子电信—信号与信息处理]