一种面向RISC体系结构的全局延迟槽调度策略  

Global Scheduling Technique of Delay Slot on RISC Architecture

作　　者：蒋奕[1] 吴承勇[1] 张兆庆[1] 冯晓兵[1] 

机构地区：[1]中国科学院计算技术研究所体系结构室,北京100080

出　　处：《计算机科学》2004年第12期192-195,共4页Computer Science

基　　金：国家863计划软件重大专项(2002AA1Z2104)的支持

摘　　要：精简指令集(RISC)体系结构常使用延迟槽来减少因分支而造成的延迟。而优化编译器如何高效地利用延迟槽对于性能来说十分重要。本文对延迟槽调度中调度范围、所处编译阶段等问题进行了分析,对全局延迟槽调度可能出现的冲突及候选指令的区域进行了探讨,并提出了一种全局延迟槽调度算法,实验结果证明了它的性能和健壮性。RISC architecture is widely adopted in processor design. Delay slot has been used in hardware to reduce latency and miss penalty of branch prediction. It is vital for an optimizing compiler to take advantage of delay slots effectively. The paper analyze the scheduling scope of delay slots, resolves possible conflicts in global scheduling of delay slots and improves the selection of instruction candidates. Then we presents a global scheduling algorithm of delay slots. The experiment results show that our approach is effective and robust.

关 键 词：延迟 RISC 调度策略 编译器 健壮性 精简指令集 体系结构 调度算法 性能 实验结果 

分 类 号：TP393[自动化与计算机技术—计算机应用技术] TP332[自动化与计算机技术—计算机科学与技术]