MPEG-4视频变长码并行解码器硬件实现  

Hardware Implementation of Parallel MPEG-4 Video Variable Length Decoder

作　　者：郑国卿[1] 虞露[1] 

机构地区：[1]浙江大学信息与通信研究所,浙江杭州310027

出　　处：《江南大学学报（自然科学版）》2004年第6期561-565,569,共6页Joural of Jiangnan University (Natural Science Edition)　

基　　金：国家自然科学基金项目(90207005);国家863项目(2002AA1Z1400)联合资助课题.

摘　　要：提出了一个MPEG 4变长码并行解码器的硬件设计.采用桶形移位器、基于PLA的并行解码算法等方法使得每个时钟周期解一个变长码码字.通过将码表改造、分割长码表为几个短码表并行查表、使用流水线技术等措施减少关键路径的延时以提高工作频率,保证了MPEG 4ASP@L5格式码流的实时解码.This paper presents a parallel design of MPEG-4 Variable Length Decoder. The design uses barrel shifter and PLA-based parallel algorithm so that one variable length code can be decoded in every clock cycle. Some special approaches, such as pipelining, reconstructing variable length code tables and partitioning a long look-up table into several shorter ones, which facilitates parallelity, are introduced. These can reduce delays on critical path, thus raising working frequency. Real-time MPEG-4 ASP@L5 decoding is ensured by the foresaid methods.

关 键 词：运动图像专家组 并行解码 改造分割码表 流水线技术 桶形移位器 

分 类 号：TN919.8[电子电信—通信与信息系统]