一种新型低压COMS四象限模拟乘法器  

A Low-voltage CMOS Four-quadrant Analog Multiplier

作　　者：宋树祥[1] 王卫东[1] 

机构地区：[1]桂林电子工业学院通信与信息工程系,广西桂林541004

出　　处：《桂林电子工业学院学报》2005年第1期35-38,共4页Journal of Guilin Institute of Electronic Technology

基　　金：广西区自然科学基金项目(D200111)

摘　　要：一种新型低压CMOS四象限模拟乘法器以源衰减器和全差分电流传输器(FDCC )为核心,当电源电压为±1.5V时,电路功耗小于75μW.该乘法器电路具有较好的线性输入范围,达到±1V,当输入电压范围限于±0.8V时,非线性误差小于0.6%,-3dB带宽约为10MHz.A low-voltage CMOS four-quadrant analog multiplier using active attenuators and FDCCⅡ is presented. Its basic configuration and design principle are analyzed. Results from PSPICE simulation show that the circuit has a power dissipation of 75μW and a full-scale linear input range about ±1V for ±1.5V power supply. The nonlinear error of the multiplier is less than 0.6% with an input range up to ±0.8V, and the simulated -3dB bandwidth is about 10MHz.

关 键 词：CMOS 有源衰减器 四象限模拟乘法器 

分 类 号：TN432.1[电子电信—微电子学与固体电子学]