Fault-Tolerant Design Techniques in ACMP Architecture  

作　　者：YAOWen.bin WANGDong-sheng 

机构地区：[1]DepartmentofComputerScienceandTsinghuaUniversity,Beijing100084,China／／ResearchInstituteofInformationTsinghuaUniversity,Beijing100084,ChinaTechnology,Technology, [2]ResearchInstituteofInformationTechnology,TsinghuaUniversity,Beijing100084,China

出　　处：《Wuhan University Journal of Natural Sciences》2005年第1期5-8,共4页武汉大学学报（自然科学英文版）

基　　金：Supported by the National High Techology Devel opment 863 Program of China(2002AA1Z030) and China PostdoctoralScience Foundation(2003034151)

摘　　要：Single-chip multiprocessor (CMP) combined with the fault-loleranl(FT)techniques offers an ideal architecture to achieve high availability on the basis of sustaining highcomputing performance FT design of a single-chip multiprocessor is described, including thetechniques from hard-wart redundancy to software support and firmware strategy. The design aims atmasking the influences of errors and automatically correcting the system states.Single-chip multiprocessor (CMP) combined with the fault-loleranl(FT)techniques offers an ideal architecture to achieve high availability on the basis of sustaining highcomputing performance FT design of a single-chip multiprocessor is described, including thetechniques from hard-wart redundancy to software support and firmware strategy. The design aims atmasking the influences of errors and automatically correcting the system states.

关 键 词：computer architecture fault-tolerant design single-chip multiprocessor 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构] TP302.8[自动化与计算机技术—计算机科学与技术]