Simultaneous Multithreading Fault Tolerance Processor  

作　　者：DONGLan HUMing-zeng JIZhen-zhou CUIGuang-zuo TANGXin-min HEFeng 

机构地区：[1]DepartmentofComputerScienceandEngineering,HarbinInstituteofTechnology,Harbin150001,Heilongjiang,China [2]ModernEducationCenterofBeijingUniversity,Beijing100086,China

出　　处：《Wuhan University Journal of Natural Sciences》2005年第1期17-20,共4页武汉大学学报（自然科学英文版）

基　　金：Supported by the National Natural Science Funda tion of China (60103002)

摘　　要：Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61%longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4%～1%to most of the benchmarks we choose randomly.Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61%longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4%～1%to most of the benchmarks we choose randomly.

关 键 词：Key words simultaneous multithreading rault tolerance TLP (Thread Level Parallelism) fetch policy 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构] TP302.1[自动化与计算机技术—计算机科学与技术]