循环移位可编程序逻辑阵列的可测试性设计  

A Testable Design of Circular-shift PLAs

作　　者：韩继国 

机构地区：[1]骊山微电子公司,陕西临潼710600

出　　处：《微电子学与计算机》1993年第9期21-23,共3页Microelectronics & Computer

摘　　要：本文研究了一种“芯片内部自测式”可编程序逻辑阵列(Built-in Sclf Tcst PLA)的设计方法:循环移位PLA(简称CS-PLA)法.CS-PLA与其他PLA可测试性设计方法相比,具有故障覆盖率高、对电路速度影响小、测试生成简单等特点,当PLA嵌入在芯片内部时,不需要单独的测试状态。其芯片面积成本随PLA的规模增大而降低,因此CS-PLA特别适用于大规模“嵌入式”PLA.In this paper we investigate a design method of a built-in self-test PLA: circular-shift PLA(CS- PLA). It offers many advantages compared to existing methods: hardware is low, testing is at normal operating speed, test generation is simple, a very wide class of faults are covered and only one self-test mode is required. It is suitable for large embedded PLAs.

关 键 词：逻辑阵列 可测试性 设计 循环移位 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]