一种兼容微处理器指令译码单元的优化设计  

Improving the Performance of the Instruction Decoding Unit in One Compatible Microprocessor

作　　者：易海峰[1] 高德远[1] 张盛兵[1] 安建峰[1] 

机构地区：[1]西北工业大学航空微电子中心,西安710072

出　　处：《微电子学与计算机》2004年第12期119-122,共4页Microelectronics & Computer

摘　　要：针对与X86微处理器兼容的32位微处理器,研究设计了一种指令译码器。X86指令集结构复杂,串行译码方式实现简单,效率不高。本文在没有更改处理器体系结构的基础之上,把译码过程分成两个步骤,用多个译码部件实现并行译码,并简要证明方案的可行性。最后用VHDL硬件描述语言实现了设计思想,能够单拍译出一条不带前缀的指令,提高了译码效率。The instruction decoder is designed for a 32bit microprocessor which is compatible with X86 series microprocessors. It is easy to decode X86 instruction set by using the serial decoding mode, but not efficient. The design of this paper divides the decoding process into two steps and uses several components to decode instructions in a parallel mode without modifying the structure of the microprocessor. We demonstrate the method is available briefly. Ultimately the decoder that is realized by VHDL can decode an instruction without prefix in a clock.

关 键 词：CISC 微处理器 指令译码 

分 类 号：TN47[电子电信—微电子学与固体电子学] TP368.1[自动化与计算机技术—计算机系统结构]