超前进位加法器混合模块延迟公式及优化序列  

Delay Time Formulae and Optimizing Sequence of Hybrid Modules Cascade Carry Lookahead Adders

作　　者：王礼平[1] 王观凤[1] 

机构地区：[1]中南民族大学电子信息工程学院,武汉430074

出　　处：《微电子学与计算机》2005年第1期152-155,共4页Microelectronics & Computer

摘　　要：为扩展操作位数提出了一种更具普遍性的长加法器结构──混合模块级联超前进位加法器。在超前进位加法器(CLA)单元电路优化和门电路标准延迟模型的基础上,由进位关键路径推导出混合模块级联CLA的模块延迟时间公式,阐明了公式中各项的意义。作为特例,自然地导出了相同模块级联CLA的模块延迟时间公式。并得出和证明了按模块层数递增级联序列是混合模块级联CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列。这一结论成为优化设计的一个设计规则。还给出了级联序列数的公式和应用实例。In order to expand operand bet of the long adders, a general structure of hybrid modules cascade Carry Lookahead Adders (CLA) was presented. It's delay time formulae which based on optimizing circuit unit and the standard delayed model of logic gate were derived from carry critical path. The meaning of all terms in the formulae was expounded. As a specific example, the delay time formulae of the same modules cascade CLA were easily derived. The increasing sequence in compliance with modular hierarchy number is speed optimizing sequence of minimum delay time, fixed resource (area) expense and power dissipation in all sequence of the hybrid modules cascade CLA. That conclusion was derived and proven. It become a design rule of optimizing design. The formula of modular cascade sequence number and an application example was given.

关 键 词：超前进位加法器(CLA) 混合模块 延迟时间公式 速度优化序列 

分 类 号：TP342.21[自动化与计算机技术—计算机系统结构]