基于PCI总线的100MSps,256MBit数据采集系统  

The 100 MSps, 256 MBit data acquisition system based on PCI bus

作　　者：王立欣[1] 刘双宝[1] 刘雷[1] 

机构地区：[1]哈尔滨工业大学电气工程及自动化学院,黑龙江哈尔滨150001

出　　处：《哈尔滨工业大学学报》2005年第2期246-248,258,共4页Journal of Harbin Institute of Technology

摘　　要：为满足高速测试装置的需要,设计并实现了以同步动态存储器 (SDRAM)为数据缓冲单元,复杂可编程器件(CPLD)为控制核心, PCI9030为PCI接口芯片的高速大容量数据采集系统. 针对SDRAM存储器控制复杂的特点,采用自顶向下的模块化设计方法,并用EDA工具综合和仿真,实现了基于CPLD的SDRAM控制器. 设计过程中,用同步状态机控制整个流程,实现了地址、数据、控制信号的可靠同步. 采集系统的软件部分由驱动程序和应用程序构成,分别用DDK和VC++软件编写. 实际测试结果表明,采集系统的最高采样频率可达 100MHz,采样容量可达 256MBit,有效位数为 7 24,达到了预期的指标.To satisfy the requirement of the high speed testing device, A high-speed and large capacity data acquisition system based on PCI bus has been proposed. With the SDRAM as data buffer cell, the CPLD as control centre, the PCI9030 as PCI interface chip, the whole system realized data storage, control and transmission. Employing the top-to-bottom design method, synthesized and simulated in the EDA environment, the SDRAM controller based on CPLD has been designed. In order to synchronize the addresses, data and controlling signals reliably, the synchronous state machine was applied to control the whole flow. The software of the sample system is consisted of the driver program arid the App program, and compiled by DDK and VC++ respectively. The tested results that the highest sample frequency is 100 MHz, the maximum storage is 256 MBit, and the effective digit of system is 7. 24 indicate, the data acquisition system has met the requirement of design.

关 键 词：PCI总线 数据采集 SDRAM CPLD 驱动程序 

分 类 号：TN919[电子电信—通信与信息系统]