基于JPEG2000的TAGTREE编码算法分析及其FPGA实现  

Analysis of TAGTREE Encoding Algorithm and its FPGA Implementation for JPEG2000

作　　者：吴宗泽[1] 郑南宁[1] 黄宇[1] 朱悦心[1] 

机构地区：[1]西安交通大学人工智能与机器人研究所,陕西西安710049

出　　处：《小型微型计算机系统》2005年第3期478-481,共4页Journal of Chinese Computer Systems

基　　金：国家"八六三"计划项目(2002AA1Z1440)资助;国家自然基金优秀创新群体项目(60024301)资助;西安市科技局创新工程项目(CX2002-10)资助.

摘　　要：详细分析了TAGTREE编码规则及其在JPEG2000中的应用,采用固定存储器地址映射关系实现子父节点对应关系的方法简化了地址发生逻辑,提出一种用于JPEG2000打包的TAGTREE编码VLSI体系结构.在Altera公司Stratix系列芯片EP1S25B672C7搭建的FPGA平台上,能够以100MHz时钟频率进行实时打包处理,全部设计只需要消耗628个逻辑单元和128字节的片内存储器.Basic regulations of TAGTREE encoder were investigated and the application of TAGTREE in JPEG2000 was analyzed in detail. A high-performance TAGTREE encoding VLSI architecture in JPEG2000 tier2 encoder was presented. The address generator was simplified by using the method that the address mapping of memory was used to specify the relation between son nodes and father nodes. By using Altera's stratix EP1S25B672C7 in FPGA platform, this design architecture could work in real time, at the clock frequency of 100MHz,with only 628 logic cells and 128 bytes memory consumed.

关 键 词：TAGTREE JPEG2000 零位平面 包含信息 打包 

分 类 号：TN402[电子电信—微电子学与固体电子学]