支持AFTER子句的综合算法研究  

Study on the Synthesis Algorithm Supporting AFTER Clauses

作　　者：程利新[1] 石峰[1] 

机构地区：[1]北京理工大学信息科学技术学院计算机科学工程系,北京100081

出　　处：《北京理工大学学报》2005年第2期116-120,共5页Transactions of Beijing Institute of Technology

基　　金：国家自然科学基金资助项目 (69973 0 0 3 )

摘　　要：为了提高综合系统的效率 ,减少对综合系统的人工干预 ,提高其自动化程度 ,对 VHDL 硬件描述语言中的AFTER子句进行研究 .通过对其行为综合语义的定义 ,给出了在 AFTER子句时延约束下的 ASAP和 AL AP算法 ,建立了 AFTER子句时延约束下的调度模型 ,并采用整数线性规划法求解调度模型 .实验结果表明 ,在综合过程中考虑 AFTER子句 ,不仅提供了一个有效给出时序约束的手段 ,而且使得设计描述方式更能够符合思维习惯 ,同时扩大了行为描述中可用语法范围 。A study on AFTER clauses in the VHDL hardware description language is presented to improve the design efficiency of HLS system, so as to decrease manual interruption and enhance the automatism of HLS system. Through the definition of behavioral synthesis meaning of AFTER clauses, the enhanced ASAP and ALAP algorithm under AFTER clause delay time constraints is presented. The scheduling model under AFTER clause delay time constraints is also presented. The scheduling model is resolved by ILP. According to experimental results presented, an effective way to set timing constraints is offered by considering AFTER clause in high-level synthesis. At the same time, the design description style can be more acceptable to the designer, and the range of available grammar in behavioral description is expanded. The ability of forecasting synthesis result is enhanced.

关 键 词：高级综合 数据路径 时序约束 

分 类 号：TP301.1[自动化与计算机技术—计算机系统结构]