3 bit块自适应量化算法的FPGA实现  

FPGA Implementation of 3 bit Block Adaptive Quantization Algorithm

作　　者：崔嵬[1] 李承恕[1] 童智勇[2] 

机构地区：[1]北京交通大学电子信息工程学院,北京100044 [2]中国科学院电子学研究所,北京100080

出　　处：《北京理工大学学报》2005年第2期139-142,共4页Transactions of Beijing Institute of Technology

基　　金：国家部委基金资助项目 (0 3 0 6.1.BQ0 10 1)

摘　　要：用现场可编程门阵列 (FPGA)对合成孔径雷达 (SAR)原始数据进行压缩能降低数据压缩时间 ,增加雷达分辨力 .针对分块自适应量化 (BAQ)算法的理论基础以及数字信号处理器 (DSP)与 FPGA各自的结构特点 ,提出了用 FPGA实现 BAQ压缩 ,并介绍了具体实现过程 .试验结果表明 ,用 FPGA实现 BAQ压缩速度快 ,电路结构简单 ,压缩后的信号保真度高 ,因此用专用集成电路对Using field programmable gate array (FPGA) for synthesized aperture radar (SAR) data compression can reduce the time of data compression, so it increases the resolution of radar. Under studying the block adaptive quantization (BAQ) algorithm and comparing the hardware structure of digital signal processor (DSP) and FPGA, the idea of using FPGA for BAQ is presented in this paper, and the detail processes of 3 bit BAQ compression implemented by FPGA are also introduced. Experimental results show that implementing BAQ compression employing FPGA has the advantages of high speed, simple circuit structure and high signal fidelity after quantization. So using application specific integrated circuit (ASIC) for SAR raw data compression will become one of efficient approaches for improving speed.

关 键 词：块自适应量化 合成孔径雷达 数据压缩 现场可编程门阵列 

分 类 号：TN402[电子电信—微电子学与固体电子学]