二维DCT算法的高速芯片设计  

FPGA Implementation of High Throughput 2D-DCT

作　　者：钟文荣[1] 陈建发[1] 

机构地区：[1]厦门大学电子工程系,福建厦门361005

出　　处：《厦门大学学报（自然科学版）》2005年第2期198-201,共4页Journal of Xiamen University：Natural Science

摘　　要：介绍了一种基于行列变换快速算法的高速DCT处理芯片的设计,并详细阐述了实现这一算法的电路结构.为了提高芯片的处理速度,电路中采用了流水线结构和双 RAM转置存储技术,并给出 FPGA实现和 Verilog综合结果.综合结果显示,该芯片最高可以工作在140 MHz的时钟频率上,非常适合于各种视频图像压缩方面的实时应用.The discrete cosine transform(DCT) has been widely used in the implementation of low bit rate codes for video compression as an integral part of several international standards.In this paper,we present a high throughput 2D-DCT architecture with circuit designs in details,based on the algorithm of matrix row-column transposition.In order to improve the throughput performance,two technologies of pipeline structure and Double RAM Buffer are employed.At the end of this paper,the FPGA implementation and Verilog synthesis results are provided,which shows that the clock rate can achieve up to 140 MHz.It is well suited for the application in real time image and video compression system.

关 键 词：DCT FPGA 芯片 设计方案 视频压缩技术 二维DCT算法 编码 

分 类 号：TN47[电子电信—微电子学与固体电子学]