集总RLC互连树的建模及门负载延迟的近似计算  

Lumped RLC Interconnect Tree Modeling and Gate Load Delay Approximate Calculation

作　　者：尹国丽[1] 林争辉[1] 

机构地区：[1]上海交通大学电子工程系,上海200030

出　　处：《计算机辅助设计与图形学学报》2005年第2期215-222,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家"八六三"高技术研究发展计划 (2 0 0 2AA1Z1190 )

摘　　要：利用一段简单的电路模型对门输出端的集总RLC互连树建模并计算门负载延迟 采用二叉树的数据结构表示集总RLC互连树 ,从而快速计算互连树入端导纳的分量 ,进一步导出Π RLC模型中的R1,L1,C1和C2 参数 ,计算出斜坡输入时的门负载延迟 实验证明 ,应用文中模型计算出的门负载延迟与Spice延迟偏差不超过 3% 。In this paper, a lumped RLC interconnect tree for gate output is modeled with a simple circuit segment, and the gate load delay is then calculated. Through the representation of the lumped RLC interconnect tree in binary tree structure, the driving point admittance moment may be rapidly obtained, and the parameters R 1, L 1, C 1 and C 2 in the Π model are deduced, then the gate load delay is obtained from ramp response. The simulation result is within 3% deviation from the one obtained with Spice, so the model proves to be feasible in gate delay estimation for design verification.

关 键 词：门负载延迟 入端导纳 分量 门延迟 转换函数 集总RLC互连树 斜坡输入 

分 类 号：TN47[电子电信—微电子学与固体电子学]