低功耗Clock-Gating技术在SAR实时成像处理中的应用  

Low Power Clock-Gating Method and Its Applications in SAR Real-Time Processor

作　　者：陈冰冰[1] 邵洁[2] 王贞松[1] 赵荣彩[3] 

机构地区：[1]中国科学院计算技术研究所,北京100080 [2]北京市遥感信息研究所,北京100085 [3]解放军信息工程大学,郑州450002

出　　处：《电子与信息学报》2005年第3期449-453,共5页Journal of Electronics & Information Technology

基　　金：国家自然科学基金重大项目(NFNS69896250-2)资助课题

摘　　要：功耗问题在SAR实时成像系统中是不容忽视的。该文以实时成像系统中的输入分机为研究平台,测试了信号处理中常用芯片DSP,SBSRM,FPGA在采用Clock-gating技术前后,功耗的变化。通过大量的实验结果,验证了Clock-gating技术在SAR实时信号处理中的可行性,对降低SAR实时成像系统,尤其是星载实时成像系统的功耗有一定的指导意义。Power consumption has to be taken into consideration in an applied SAR real-time processor. The power consumption is measured before and after clock-gating method had been applied to DSP, SBSRAM and FPGA of an air-borne SAR real-time preprocessor board respectively by software. It has been proved that clock-gating method is feasible for low power design in the SAR especially the future space-borne SAR real-time processor.

关 键 词：SAR实时成像处理 低功耗 Clock-gating技术 

分 类 号：TP752[自动化与计算机技术—检测技术与自动化装置]