Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction  

作　　者：Yin-HeHan Xiao-WeiLi Hua-WeiLi AnshumanChandra 

机构地区：[1]InstituteofComputingTechnology,ChineseAcademyofSciences,Beijing100080,P.R.China／／GraduateSchoolofChineseAcademyofSciences,Beijing100039,P.R.China [2]InstituteofComputingTechnology,ChineseAcademyofSciences,Beijing100080,P.R.China [3]Synopsys,Inc.,700E.MiddlefieldRd.,MountainView,CA94043,U.S.A.

出　　处：《Journal of Computer Science & Technology》2005年第2期201-209,共9页计算机科学技术学报（英文版）

基　　金：国家自然科学基金，the Sci. & Technol. Project of Beijing，中国科学院资助项目，Synopsys公司资助项目

摘　　要：This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratios can be obtained even for chips with a small numberof outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnosticability, minimize error cancellation and handle unknown bits in the outputs of the circuit undertest (CUT). The q-Compactor can also be moved to the load-board, so as to compact the outputresponse of the CUT even during functional testing. Therefore, the number of tester channelsrequired to test the chip is significantly reduced. The experimental results on the ISCAS ''89benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is veryefficient.

关 键 词：system-on-a-Chip (SoC) test resource partitioning (TRP) responsecompaction DIAGNOSE error cancellation 

分 类 号：TN407[电子电信—微电子学与固体电子学]