A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead  

作　　者：AbdilRashidMohamed ZeboPeng PetruEles 

机构地区：[1]DepartmentofComputerandInformationScience,LinkSpingUniversity,S-58183,Sweden

出　　处：《Journal of Computer Science & Technology》2005年第2期216-223,共8页计算机科学技术学报（英文版）

摘　　要：This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.

关 键 词：BIST insertion test synthesis wiring area simulated annealing 

分 类 号：TN407[电子电信—微电子学与固体电子学]