A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock  

作　　者：Yin-ShuiXia Lun-YaoWang A.E.A.Almaini 

机构地区：[1]SchoolofEngineering,NapierUniversity,10ColintonRoad,EdinburghEHIO5DT,U.K.／／SchoolofInformationandEngineeringScience,NingboUniversity,Ningbo315211,P.R.China [2]SchoolofInformationandEngineeringScience,NingboUniversity,Ningbo315211,P.R.China [3]SchoolofEngineering,NapierUniversity,10ColintonRoad,EdinburghEHIO5DT,U.K.

出　　处：《Journal of Computer Science & Technology》2005年第2期237-242,共6页计算机科学技术学报（英文版）

基　　金：国家自然科学基金，国家自然科学基金

摘　　要：A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.

关 键 词：CMOS flip-flops multiple-valued clock multiple-valued logic 

分 类 号：TN432[电子电信—微电子学与固体电子学]