DSPs实时视频处理中的Cache优化算法研究  

Optimization Algorithm for Cache in Real-Time Video Processing Based on DSPs

作　　者：唐文佳[1] 朱光喜[1] 王曜[1] 刘瑜[1] 

机构地区：[1]华中科技大学电子与信息工程系宽带与多媒体研究中心,湖北武汉430074

出　　处：《小型微型计算机系统》2005年第4期680-683,共4页Journal of Chinese Computer Systems

基　　金：国家"八六三"项目(2002AA119010)资助.

摘　　要：在采用并行超长指令字结构的DSP芯片中,CPU处理速度与片外数据存取速度不匹配的问题,导致了CPU处理延时,限制了DSP系统性能的提升.针对这一问题,根据Cache的结构提出一种适宜于在DSPCPU上进行视频数据处理的数据排列新算法,并且将其成功地应用到基于TrimediaPNX1301的MPEG4程序优化工作中.系统编码结果表明,该方法有效地减少了Cachemiss及片外数据存取的时间开销,在同等条件下,采用本算法后系统编码性能提高2帧/秒(CIF格式)左右.In VLIW DSPs, a problem is that the speed of CPU processing is not compatible with that of the off-chip accesses to main memory, which is responsible for CPU process delay,Thus it becomes a bottleneck of DSP performance. This paper provides a new data-layout algorithm for video data processing based on DSP CPU according to the Cache Architecture. And it is applied to the optimization work of MPEG-4 program based on Trimedia PNX1301 successfully. The encoding results demonstrate the effectiveness of this algorithm in eliminating Cache misses and Cache bank conflicts. Meanwhile, it reduces the cost of off-chip accesses. And the encoding performance has increased about 2f/s(CIF) with this algorithm.

关 键 词：CACHE优化 数据排列算法 MPEG-4视频编码器 DSPs优化 

分 类 号：TN911[电子电信—通信与信息系统]