一种低功耗高精度CMOS动态比较器设计与实现  

Design and Implementation of a Low Power Dissipation High Accuracy CMOS Dynamic Comparator

作　　者：张文忠[1] 包兴[1] 姚素英[1] 李树荣[1] 徐江涛[1] 

机构地区：[1]天津大学专用集成电路设计中心,天津300072

出　　处：《传感技术学报》2005年第1期132-135,139,共5页Chinese Journal of Sensors and Actuators

基　　金：天津市科委科技攻关基金项目 (0 33183911)

摘　　要：设计了一种全差分动态比较器。比较器是前置放大器与动态锁存器组成的开关电容电路。在四相互不交叠时钟控制下 ,前置放大器完成对输入信号采样、放大 ,高增益提高了比较器的精度 ,采用正反馈结构提高了比较器的速度。文中分析了引起失调的原因 ,结合版图给出了减小失调的方法。分析和模拟结果表明比较器输入动态范围为 2V ,失调电压降低到 3 5mV ,达到了 8bit精度要求 ,同时实现了 0 . 4 8mW的功耗。A full differential dynamic comparator is designed. It is a switch capacitor circuit which consists of the preamplifier and dynamic latch. Sampling and amplifying of the input signals can be achieved by preamplifier with the control of four phase non-overlap clock. High gain improves the accuracy of the comparator and positive feedback increases the speed of it. With analysis of the factors which cause offset, improving method based on layout design is presented. Analysis and simulation results indicate that the input dynamic range is 2 V, input offset voltage reduces to 3.5 mV, 8 bit resolution is achieved, and the power dissipation is 0.48mW.

关 键 词：动态比较器 开关电容 流水线ADC 失调电压 

分 类 号：TN79[电子电信—电路与系统] TP212[自动化与计算机技术—检测技术与自动化装置]