CMOS门阵列纠错编码电路  

CMOS Gate Array Implementation of Error Detection and Correction Units

作　　者：扬樱华 黄锡孙 赵淑嫒 许娟 李明扬 

机构地区：[1]骊山微电子学研究所

出　　处：《微电子学与计算机》1989年第5期1-5,共5页Microelectronics & Computer

摘　　要：本文介绍采用CMOS门阵列技术实现的、用于容错存储体的两种纠错编码电路(奇权纠错编码电路及多位纠错编码电路)的设计与实现。这两种电路均已研制成功并已通过部级鉴定。In this paper, we present the design and implementation by CMOS gate arrays of error detection and correction units of fault-tolerant memory systems. Two kinds of units, corresponding to two kinds of error correcting codes——odd weight code (single bit error correction and double bit error correction) and single byte error correcting Reed—Solomon Code. have been developed.The results of this research work have received complimentary approval from the Ministry of Aero-Astronautics.

关 键 词：CMOS门阵列 纠错编码电路 

分 类 号：TN911.22[电子电信—通信与信息系统]