一款嵌入式芯片总线仲裁器的设计和评估  

Design and Evaluation of SoC Bus Arbiters

作　　者：鲍胜荣[1] 吴旭凡[1] 钟锐[1] 

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,江苏省南京市210096

出　　处：《电子工程师》2005年第1期19-22,共4页Electronic Engineer

摘　　要：针对片上系统(SoC)总线设计中仲裁机制的选取往往局限于抽象的定性分析,以一款嵌入式处理器芯片为设计平台,实现了固定优先级、轮转优先级和混合优先级的仲裁电路设计,并建立了仿真测试平台,通过仿真对总线主设备的总线占有率、最差等待响应时间进行了定量分析比较,得出了混合优先级仲裁机制较单一的固定优先级与轮转优先级仲裁机制在体现公平性与优先性上更有效的结论,对其他嵌入式系统总线的仲裁设计与改进提供了很好的参考。Due to selection uncertainty of arbitration mechanisms in the design of SoC bus, our design platform is based on an embedded processor. Three arbitration mechanisms, including fixed priority, rotating priority and mixed priority are implemented. By establishing a test bed based on Garfield SoC and comparing simulated results, the bus performance including bus bandwidth, worst latency is evaluated. Evaluation result shows that mixed-priority arbitration mechanism is better than the other two arbitration mechanisms in terms of fairness and priority. The conclusion can be used as a good reference as far as other arbiter design is concerned.

关 键 词：仲裁器 SOC 嵌入式处理器 评估 响应时间 

分 类 号：TN492[电子电信—微电子学与固体电子学]