基于FPGA的高速高斯随机数发生器  

High-speed Gaussian Random Number Generator Implemented with FPGA

作　　者：陆兴平[1] 许拔[1] 

机构地区：[1]国防科学技术大学电子科学与工程学院,湖南长沙410073

出　　处：《现代电子技术》2005年第9期88-90,共3页Modern Electronics Technique

摘　　要：设计了一个基于FPGA的高速、高性能的高斯随机数发生器。首先简要介绍了以前的一些算法并指出其不足之处。然后阐明了本文的算法:对均匀随机数进行高效的变换以生成非常接近高斯分布的随机数,再依据中心极限定理把两个上述随机数相加得到高斯随机数。算法所需的运算只有RAM的读操作与乘法、加法运算。分析了算法的性能并与其他算法做了对比,证明了本文算法的高效性。最后给出了FPGA实现的系统结构,并分析了所需的硬件资源。A highspeed gaussian random number generator implemented with FPGA is presented in this paper.Several algorithms are briefly introduced and their shortcomings are pointed out.Then algorithm is presented: firstly,uniformlydistributed random numbers are effectively transformed to 'GaussianLike' numbers,secondly,based on central limit theorem,each two of such 'GaussianLike' numbers are added together to generate a gaussian sample.All the operations needed are addition,multiplication and RAM reading.The performance of the generator is excellent compared with others.Finally the system structure in FPGA is given.

关 键 词：正态分布 随机数发生器 FPGA RAM 

分 类 号：TN782[电子电信—电路与系统]