JPEG解码器的软硬件协同设计  

Hardware/Software Cooperative Design for JPEG Decoder

作　　者：刘洋[1] 陈杰[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2005年第3期23-27,共5页Microelectronics & Computer

基　　金：国家863项目"32位高性能嵌入式数字信号处理器(DSP)芯片设计与实现"(2002AA1Z1130)

摘　　要：JPEG压缩标准已被广泛的应用于数码相机、图像网络传输等众多领域,实时处理对JPEG解码器提出了更高的要求。本文设计出适合JPEG快速解码的嵌入式可重构32位DSP(DigitalSignalProcessing),并基于此款DSP结构对JPEG解码器进行了系统和局部的优化。实际测试结果显示,相比传统的解码器,改进后的JPEG解码器平均解码周期降低了80%左右。JPEG compression standard has been widely used in many fields such as digital still image, image transmission via network. It requires better performance for decoders in real-time processing. In this paper, a reconfigurable embedded 32-bit digital signal processor has been designed to fast decode. And based on the architecture of this DSP, optimizations on the system and parts have been done on JPEG decoder. Experimental results show that the average decoding cycles reduce by 80 percent, compared with that of traditional decoder.

关 键 词：DSP处理器 JPEG 图像解码 

分 类 号：TN919.81[电子电信—通信与信息系统]