一种数字调谐系统专用频率合成芯片的设计  

Design of PLL Frequency Synthesizer for Digital Tuning System

作　　者：刘莎[1] 卢雪萍[1] 马骏[1] 

机构地区：[1]杭州电子工业学院IC-CAD研究所,浙江杭州310037

出　　处：《电声技术》2005年第4期31-33,共3页Audio Engineering

摘　　要：针对一个汽车音响收音数字调谐系统的实例,介绍了一种广播用双波段锁相环频率合成芯片的设计方法。其中采用串行端口按位传输数据的方式,在程序分频器部分使用了吞脉冲技术,不仅简化了控制器的操作,同时也获得了较高的频率分辨力,实际产品具有广泛的市场前景。A Phase Locked Loop (PLL) Frequency Synthesizer for Digital Tuning System (DTS) is presented, which is applied to DTS of car radio receiver. In which, a format for serial data transmission and a pulse-swallow method for programmable divider are adopted. Not only the operation of MCU is simplified, but also high frequency resolution is achieved. The practical product has good market potential.

关 键 词：数字调谐系统 锁相环频率合成器 吞脉冲计数器 串行数据传输 

分 类 号：TN742.1[电子电信—电路与系统]