基于WDC结构的低静态功耗Cache设计  

Cache Design for Low Leakage Power Based on Way-Decay Cache

作　　者：鲁欣[1] 付宇卓[1] 

机构地区：[1]上海交通大学微电子学院,上海200030

出　　处：《上海交通大学学报》2005年第4期606-609,613,共5页Journal of Shanghai Jiaotong University

基　　金：国家高技术研究发展计划(863)项目(2003AA1Z1350)

摘　　要：基于片上cache占处理器芯片功耗的比重越来越大,提出了一种新的路衰减cache(Way-DecayCache,WDC)结构.该结构通过门控Gnd技术来动态地关闭或开启部分cache路,使得cache结构可以在低功耗配置和正常配置之间切换,从而达到降低静态功耗的目的.与现有的低功耗cache结构相比,附加的逻辑少,实现简单,具有硬件的可实现性.试验结果表明,该结构可以降低cache的功耗,同时对cache整体的性能影响很小.The power dissipation of cache on chip is the main part of entire processor chip dissipation, so this paper proposed a new WDC (Way-Decay Cache). This novel cache architecture can turn off some unused ways and run in configuration with low power, otherwise it runs in normal configuration, so it can reduce the average leakage power. Compared with the current cache architecture for low power, this architecture with resizable ways and low leakage power has the characteristic of fewer additional logics, simpler implementation and better hardware implementation. The experiments show the architecture can decrease energy consumption without significantly hindering performance.

关 键 词：路衰减cache 门控Gnd 低静态功耗 

分 类 号：TN492[电子电信—微电子学与固体电子学] TP302.1[自动化与计算机技术—计算机系统结构]