一种IEEE 802.11b基带处理器的低硬件复杂度设计  

The design of an IEEE 802.11b baseband processor with reduced hardware complexity

作　　者：涂春江[1] 周欣[1] 刘伯安[1] 陈弘毅[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《清华大学学报（自然科学版）》2005年第4期557-560,共4页Journal of Tsinghua University(Science and Technology)

基　　金：国家"八六三"高技术项目(2002AA1Z1380)

摘　　要：为了降低基带处理器的硬件复杂度以减少系统的成本,该文提出了一种适用于IEEE802.11b的基带处理器设计。重点描述了捕获、同步以及补偿码键控(CCK)解调方法。在捕获和同步过程中,采用了天线锁定技术,并且利用一种特殊转置结构的相关器完成了信号检测功能。CCK解调器包含快速Walsh变换(FWT)结构和符号判决单元,采用了一种新的算法和结构,降低了硬件复杂度。该芯片采用TSMC公司的0.25μm逻辑CMOS工艺设计,等效门数为32万门,版图面积为13mm2,仿真验证表明新的设计降低了硬件复杂度。A low-hardware-complexity baseband processor was designed to reduce the cost of the IEEE 802.11b WLAN system. The baseband processor includes synchronization, acquisition, and complementary code keying (CCK) demodulation. The correlator uses a transposed architecture for signal acquisition and synchronization. The antenna lock technique during acquisition is also described. The CCK demodulator is based on a Fast Walsh Transform (FWT) block, with a novel algorithm used to reduce the hardware complexity. After simulation and verification, the chip was designed using 0.25 μm TSMC digital CMOS technology. The design has about 320 000 gates and a chip area of about 13 mm^2. The simulation results show that the design satisfies all the design requirements.

关 键 词：数据处理 基带处理器 无线局域网 IEEE 802.1lb 

分 类 号：TN919.5[电子电信—通信与信息系统]