低功耗绝热SRAM  

A Novel Low-Power Adiabatic SRAM

作　　者：董惠英[1] 胡建平[1] 蓝艇[1] 

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211

出　　处：《微电子学与计算机》2005年第4期63-66,共4页Microelectronics & Computer

摘　　要：文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.A novel adiabatic SRAM is designed. An adiabatic line driver is presented, which hasn't non-adiabatic loss on output loads by using feedback from the next-stage buffer. The adiabatic driver was used to recover the charge of large switching capacitance on the bit-lines and word-lines in fully adiabatic manner. The power consumption of the SRAM is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. The energy and functional simulation is performed. The HSPICE simulation result indicates energy savings of 75% to 85% as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200Mhz.

关 键 词：绝热电路 低功耗 SRAM VLSI设计 

分 类 号：TN431[电子电信—微电子学与固体电子学]