EPP并行通信接口同步设计  

Synchronous Design of Enhanced Parallel Port

作　　者：梁婕[1] 高德远[1] 张盛兵[1] 段然[1] 

机构地区：[1]西北工业大学计算机学院,陕西西安710072

出　　处：《计算机应用研究》2005年第6期196-198,共3页Application Research of Computers

基　　金：国防预研基金资助项目(41308010307)

摘　　要：针对异步器件在工程实践中难以控制时序,并且EDA工具所给予的支持也不如同步器件等特点,提出了一种以状态机为控制核心的同步化EPP并行通信接口的设计思路,使EPP协议的操作时序更加清晰、易于控制,电路更加稳定、可靠。此设计思路也可以推广到PS/2和ECP等并行接口的同步化设计。Due to the facts that it is more difficult to control the timing of asynchronous devices and less support from EDA tools compared with synchronous device, presents a design of synchronous Enhanced Parallel Port(EPP) based on FSM, which makes the timing of EPP more clear and controllable, and the circuits more stable and reliable.The method can also be applied to designing synchronous PS/2, Extended Capabilities Port(ECP), etc.

关 键 词：EPP 并行接口 状态机 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]