一种2.4GHz的CMOS注入锁频倍频器  

A 2.4GHz CMOS Injection-Locked Frequency Doubler

作　　者：衣晓峰[1] 苏彦锋[1] 朱臻[1] 洪志良[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《Journal of Semiconductors》2005年第5期1049-1053,共5页半导体学报（英文版）

摘　　要：介绍了一种用于频率综合器的2 .4GHz CMOS注入锁频倍频器的设计和实现.从理论上重点分析了模拟倍频器的锁频范围和相位噪声特性.当电源电压为3 3V,输入信号为400mV时,电路输出幅度为1. 04V,功耗为4. 95mW,未经电容阵列补偿时倍频器的锁频范围达到113 .7MHz.电路应用在单片集成的蓝牙发接器中,通过频率测试验证了电路功能的正确性.Introduce the design and implementation of a 2.4 GHz CMOS injection-locked frequency doubler,focusing on the theory analysis of locking range and phase noise performance of the frequency doubler.In simulation,the supply voltage is 3.3V,the amplitude of output signal can achieve 1.04V while the amplitude of input signal is 400mV,the power consumption is 4.95mW,locking range is 113.7MHz without the compensation of capacitor array.The doubler is used in a full integrated Bluetooth transceiver.Test results verify the correctness of frequency doubler’s function.

关 键 词：注入锁频倍频器 锁频范围 相位噪声 频率综合器 

分 类 号：TN771[电子电信—电路与系统]