一种新结构异步FIFO的ASIC设计  

ASIC Design of a Novel Structure Asynchronous FIFO

作　　者：周磊[1] 朱礼安[1] 苏俊杰[1] 丁晓磊[1] 赵梅[1] 顾皋蔚[1] 朱恩[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏南京210096

出　　处：《南京师范大学学报（工程技术版）》2005年第2期14-17,共4页Journal of Nanjing Normal University(Engineering and Technology Edition)

基　　金：国家"八六三"计划资助项目(2001AA121074).

摘　　要：介绍了一种新结构异步FIFO(FirstInFirstOut)电路的实现方案,运用整体移位实现数据正确写入和输出,使用缓冲寄存器组存放移位产生的多余数据,适用于频率不成整数倍的异步时钟域之间的数据传输.利用串联的D触发器作为同步器,避免产生亚稳态,实现异步信号的同步.采用自顶向下、基于0.18μm标准单元库的半定制ASIC(ApplicationSpecificIntegratedCircuit)流程对其进行设计:使用Verilog硬件描述语言,利用VCS及Modelsim进行时序和功能仿真、SynopsysDC完成逻辑综合、ApolloⅡ实现自动布局布线.将该方案与传统的异步FIFO实现方案进行比较,面积大约缩小一半,工作速度提高约三分之一.The paper presents a scheme of realizing novel asynchronous FIFO (First In First Out) structure circuit. In this scheme, unitary shift is used to realize data's correct read-in and output, and buffers are used to store the left data of unitary shift. This design is applicable for data transmission between clocks not integral multiple. Synchronizer of D triggers in series is used to avoid instability and synchronize asynchronous signals. This circuit is designed with semi-custom ASIC (Application Specific Integrated Circuit) flow which is based on top-down flow and 0.18μm digital standard cell library. The design uses Verilog hardware language, adopts VCS and Modelsim to simulate, Synopsys DC to realize logic synthesis and Apollo II to achieve automatic placing and routing. Compared with traditional asynchronous FIFO structure, it shows better performance not only on area (with about half acreage) but on speed (one third faster) as well.

关 键 词：异步FIFO ASIC 整体移位 缓冲寄存器组 

分 类 号：TN432[电子电信—微电子学与固体电子学]