基于UML时序图的集成测试序列自动生成  

Automatic Generation of Integration Test Sequences Based on UML Sequence Diagrams

作　　者：马伟[1] 张毅坤[1] 

机构地区：[1]西安理工大学计算机科学与工程学院,西安710048

出　　处：《计算机工程与应用》2005年第19期108-111,共4页Computer Engineering and Applications

基　　金：陕西省教育厅科研基金(编号:00JK265)

摘　　要：该文研究了基于UML时序图的集成测试序列自动生成方法。该方法分析了时序图的语义信息并添加语义约束规约生成可测试模型,从中提取相关信息生成有限状态机;然后使用Wp方法构造测试序列;最后使用中国邮递员算法对Wp方法进行改进生成最优测试序列。该方法生成的测试序列长度相对较短,并能充分满足测试用例覆盖需求。This paper explores an approach to automatic generation of integration test sequences based on UML sequence diagrams.The approach analyzes the semantics of sequence diagrams and adds semantic constraint specification to generate testable model.Corresponding information is abstracted from the model to generate FSM.Then,test sequences are constructed by using Wp method.Finally,authors optimize Wp method and generate optimization test sequences by using Rural Chinese Postman algorithm.The generated test sequences can fulfill adequately coverage requirement and the length of test sequences is relative short.

关 键 词：集成测试 测试序列自动生成 时序图 Wp方法 中国邮递员算法 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]