组合逻辑电路多故障测试生成算法的研究  

The research of multi - fault test generation for combinational logic circuits

作　　者：吴丽华[1] 商庆华[2] 俞红娟[1] 

机构地区：[1]哈尔滨理工大学测控技术与通信工程学院,黑龙江哈尔滨150040 [2]哈尔滨理工大学电气工程学院,黑龙江哈尔滨150040

出　　处：《电机与控制学报》2005年第4期345-348,共4页Electric Machines and Control

基　　金：黑龙江教育厅基金项目(10541040)

摘　　要：针对布尔差分算法需要进行大量的异或运算,特别是求解多故障测试矢量时,求解高阶布尔差分更是繁琐的问题,依据卡诺图求解异或运算的方法,提出了获得多故障测试矢量的简便算法。该算法对单故障特别是多故障的测试矢量生成,无论故障数为多少,只要函数的变量数不变,就不会因故障数增加而使卡诺图法的求解难度增加,从而减少了多故障测试矢量生成时间。For the problem that the Boolean difference algorithm need many exclusive OR operations, especially for the solution of multiple stuck - at faults test generation. This paper is based on the Karnaugh map to do the exclusive OR operation, and presents a simplified method of multiple stuck - at faults test generation for combinational circuits by the research of the Boolean difference algorithm. This method is not more difficult when increasing the multiplicity of the targeted fault, if only the number of variable for function is not changed. So that time for multi - fault test generation is much shorter.

关 键 词：组合电路 布尔差分 测试生成 卡诺图 

分 类 号：TN407[电子电信—微电子学与固体电子学]