基于RSA算法的大数乘法器设计  

The Design of Large Number Multiplier for RSA Algorithm

作　　者：蔡敏[1] 史伟伟[1] 黄明文[1] 

机构地区：[1]华南理工大学物理科学与技术学院,广州510641

出　　处：《半导体技术》2005年第8期65-68,共4页Semiconductor Technology

基　　金：2003年教育部科学技术研究重点项目(03130)

摘　　要：提出了普通阵列乘法电路的改进结构和含流水线的串并乘法电路(SPM)结构。后者比基于Booth算法的n位并行乘法电路更节省资源消耗,由O(n2)降低到O(n),同时相比于n位普通移位乘法器,运算时间复杂度由的O(n2)降低到O(n),且其串行输出特性更适合应用于大数乘法电路。Two circuit structures which are the optimized multiplier with full-adder array and the serial-parallel multiplier with pipeline inside are put forward. The latter reduces the consumption of resource from O(n2) to O(n) in contrast to the n-bit multiplier based on Booth algorithm. Meanwhile, comparing to the shift-add multiplier, it speeds up the computation from the time complexity O(n2) down to O(n). Further more, its serial output characteristic makes it more suitable for large number multiplier.

关 键 词：里维嘶特-沙米尔-阿德莱曼算法(RSA) 乘法器 集成电路 流水线 

分 类 号：TP342.22[自动化与计算机技术—计算机系统结构]