AMBA2.0总线IP核的设计与实现  

Design and Implementation of the AMBA 2.0 IP Core

作　　者：刘军[1] 郭立[1] 段勃[1] 白雪飞[1] 

机构地区：[1]中国科学技术大学电子科学与技术系,安徽合肥230026

出　　处：《微电子学与计算机》2005年第6期145-148,共4页Microelectronics & Computer

摘　　要：文章采用Top-Down的方法设计了AMBA2.0总线IP核,它包括AHB和APB两个子IP核。所有AMBA结构模块均实现了RTL级建模,对其中较复杂的仲裁器和AHB/APB桥模块给出了详细的描述。该IP完成了FPGA的验证,最高频率为53.6MHz。在ASIC0.18μm标准单元库下对该IP进行综合与优化,最高频率可以达到150MHz。This paper presents the Top-Down methodology design of the AMBA 2.0 architecture which is comprised of AHB and APB. The paper describes all components by RTL models and focuses on the key modules: the arbiter and the AHB/APB bridge. The architecture has been implemented on FPGA at a frequency of 53.6MHz. The RTL model of the architecture has also been synthesized using 0.18μm library and its highest frequency could get 150MHz.

关 键 词：AMBA 2.0 片上总线 AHB仲裁器 AHB/APB桥 

分 类 号：TN402[电子电信—微电子学与固体电子学]