ASIC逻辑综合中重定时序  

Retiming in Logic Synthesis of ASIC

作　　者：柳进[1] 王义和[1] 叶以正[1] 

机构地区：[1]哈尔滨工业大学

出　　处：《计算机工程与设计》1995年第1期23-28,共6页Computer Engineering and Design

摘　　要：本文针对在ＡＳＩＣ逻辑综合结构级优化中，去除冗余逻辑结构后，组合逻辑电路上可能出现的时间延迟不一致现象，导致时序混乱，使时序正常操作的限定条件不满足，这就需要重新安排和分配时序。本文分析组合逻辑电路的结构，提出了调整方法，应用二阶段线性规划方法求出最优解，为ＡＳＩＣ逻辑综合中时序的正常化提供了最佳方案。This paper mainly solves the problem of competition and adventure of combinatory circuit. Because the phenomenon of discrepancy among the delay in combinatory circuit after the structure optimization in logic synthesis, the structure of the circuit is analysized and the method of adjusting is given by adding buffers in short path. In concrete realization, we use the knowledge of data structure to find the critical short path to add buffers, set up mathematical models and finally get optimal solution by using the method of linear programing of two stages. All above supplied us the best answer of the normal execution of sequential circuit in logic synthesis of ASIC.

关 键 词：专用集成电路 逻辑综合 组合最优化 

分 类 号：TN4[电子电信—微电子学与固体电子学]