基于准浮栅技术的超低压运算放大器  

Ultra-low voltage operational amplifier based on quasi-floating gate transistors

作　　者：杨银堂[1] 任乐宁[1] 付俊兴[1] 

机构地区：[1]西安电子科技大学微电子研究所,陕西西安710071

出　　处：《西安电子科技大学学报》2005年第4期501-503,527,共4页Journal of Xidian University

基　　金：国家自然科学基金资助项目(90207022)

摘　　要：分析了准浮栅晶体管的工作原理、电气特性及其等效电路,基于准浮栅PMOS晶体管,设计了超低压低功耗运算放大器.基于台积电的0.25μmCMOS工艺,利用Hspice对所设计的运放进行了模拟仿真.仿真结果显示,在0.8V的单源电压下,运算放大器的最大开环增益为76.5dB,相位裕度为62,°单位增益带宽为2.98MHz,功耗仅为9.45μW.The fundamental principle of quasi-floating gate transistors, along with the electrical characteristics and equivalent circuits, ave discussed. An ultra-low voltage operational amplifier is proposed using the PMOS quasi-floating gate transistors. Based on the TSMC 0. 25μm CMOS process, the whole circuit is simulated by using the Hspice simulator. The simulation result shows that, with a single power supply of 0.8 V, the maximal open-loop gain of the amplifier is 76.5 dB, the phase margin is 62°, the unit gain band width is 2.98 MHz and the power dissipation is only 9.45μW.

关 键 词：准浮栅 超低压 运算放大器 CMOS 

分 类 号：TN722.77[电子电信—电路与系统]