时序逻辑电路的卡诺图分析法  

A Method of Using the Karnaugy Map to Analyse the Sequential Logical Circuit

作　　者：赵兴强[1] 金洪颖[1] 

机构地区：[1]西华师范大学计算机学院,四川南充637002

出　　处：《通化师范学院学报》2005年第4期33-36,共4页Journal of Tonghua Normal University

基　　金：四川省重点科技项目(02GG006-036)

摘　　要：提出了一种分析时序逻辑电路功能的新方法:利用分项满足法和时钟方程来填写状态方程的卡诺图。The new method was proposed which analyses the function of sequential logical circuit： Karnaugy map of the state equation was filled in by utilizing dividing term - meeting method and clock equation, and the transition map of the state is drawn directly by Karnaugy map.

关 键 词：时序逻辑电路 卡诺图 状态转换图 时钟方程 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]