ASIC逻辑综合中重定时序  

Retiming in Logic Synthesis of ASIC

作　　者：柳进[1] 王义和[1] 叶以正[1] 

机构地区：[1]哈尔滨工业大学

出　　处：《系统工程与电子技术》1995年第7期40-45,共6页Systems Engineering and Electronics

摘　　要：在ＡＳＩＣ逻辑综合结构级优化中，去除冗余逻辑结构后，组合逻辑电路上会出现时间延迟不一致性现象，导致时序混乱，使时序正常操作限定条件不满足，这样需要重新安排和分配时序。本文分析组合逻辑电路的结构，提出了调整方法，应用二阶段线性规划方法求出最优解，为ＡＳＩＣ逻辑综合中时序正常地运行提供了最佳方案。This paper mainly solved the problem of competition and adventure of combinatory circuit.Because the phenomenon of discrepancy among the delay in combinatory circuit arter the structure optimization in logic systhesis,the structure of cornbinatory circuit are analysized and the method of adjusting is given by adding buffers in short path,in concrete realization.we use the know-ledge of data structure,to find the critical short path for determation of the position to add buffers in short path.set up rnathematical model,and finally got optimical solution by using the method of linear programing of two stages(i.e delay values of the buffers added in short path)All above supp-lied us the best answer of the normal exection of sequetical circuit in logic synthesis of ASIC.

关 键 词：专用集成电路 逻辑综合 时序 ASIC 

分 类 号：TN403[电子电信—微电子学与固体电子学]