容错多Transputer体系结构  

FAULT-TOLERANT MULTI-TRANSPUTER ARCHITECTURE

作　　者：莫倩[1] 窦文华[1] 王恺[1] 肖刚[1] 

机构地区：[1]国防科技大学计算机系

出　　处：《小型微型计算机系统》1995年第6期12-17,共6页Journal of Chinese Computer Systems

摘　　要：本文提出了一种容错的多Ｔｒａｎｓｐｕｔｅｒ的体系结构。该体系结构采用并行处理芯片Ｔｒａｎｓｐｕｔｅｒ作为基本处理单元，利用多Ｔｒａｎｓｐｕｔｅｒ并行处理系统的并行性、可拓扑性，用软件实现了带一个后援备份的三倍任务仿作的动态混合冗余，达到了高可靠性的目标。在保证高可靠性的前提下，该体系结构还使资源的消耗最少。该体系结构能连续容忍系统处理单元的单故障，并自动地启动后援备份进行重构，具有很高的可靠性、实时响应能力、可配置性和可扩充性。This paper proposed a fault - tolerant multi-transputer architecture. The proposed architecture uses parallel processor transputer as the basic processing component, takeadvantage of the parallelism and reconfiguration of multi-transputer parallel systems, andachieve high reliability at low cost by the means of dynamic hybrid redundancy with a backupsparing component. The proposed architecture is capable of continuously toleranting singlefailure of processing components, automatically reconfiging transputer components by starting the backup sparing component. The advantages of this architecture are high fault tolerancy, real-time responsibility and extendibinty.

关 键 词：容错 混合冗科 体系结构 计算机系统 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]