使用三位三阶Δ∑调制器的集成1GHz小数频率合成器  

1GHz Monolithic Fractional-N Frequency Synthesizer with a 3-b Third-Order Delta-Sigma Modulator

作　　者：池保勇[1] 朱晓雷[1] 黄水龙[2] 王志华[2] 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]清华大学深圳研究生院,广东深圳518057

出　　处：《电子学报》2005年第8期1492-1496,共5页Acta Electronica Sinica

基　　金：国家自然科学基金(No.90407006);国家重大基础研究(973)项目(No.G2000036508)

摘　　要：本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μmCMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.A 1GHz monohthic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order modulator is implemented. A combined tuning technique of analog tuning and digital tuning is used to improve the phase noise of the frequency synthesizer. The power supply configuration is optimized to reduce the supply noise coupling, to improve the hnearity of PFD and to increase the tuning range of the VCO.The on-chip VCO with a small gain utihzes the tail current source filtering technique to achieve a low phase noise, but it still keeps 100MHz tuning range due to the introduction of the on - chip digital controlled switched capacitor array.The frequency synthesizer has been integrated on one chip in 0.18μm CMOS process, the simulated results show the frequency synthesizer has a 14kHz loop bandwidth and a high spectrum purity, the maximum in - band phase noise is - 106dBc/Hz, the phase noise is lower than - 120dBc/Hz at 100kHz offset,and the frequency synthesizer has a fast settling time which is about 160μs.

关 键 词：△∑调制器 频率合成器 压控振荡器 锁相环 

分 类 号：TN791[电子电信—电路与系统]