多端互连线网络布线时延的研究  

Study of Multiport Interconnection Delay

作　　者：俞惠[1] 许永生[1] 石春琦[1] 赖宗声[1] 陶永刚[1] 金玮[1] 洪亮[1] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062

出　　处：《电气电子教学学报》2005年第4期47-50,91,共5页Journal of Electrical and Electronic Education

基　　金：上海市科委资助项目(AM0308&NO.037062010)

摘　　要：互连线时延是集成电路设计中非常重要的影响因素。本文根据Elmore延迟模型推导出多端互连线的延迟估算公式,得出了在满足设计规则的前提下,多端互连线网络应尽量遵守的布线规则,即互连线之间不要有重叠,且从源点到每个终点都要走最短的曼哈顿路径。这种布线规则可以在不增加芯片面积的基础上使互连线时延减少,这对指导高速IC芯片的版图设计有重要的理论和实践指导意义。Interconnection delay has become a dominant factor in IC design. Based on Elmore delay model, we Present a new approximation method for multiport interconnection delay calculation. That is besides following the design rule, there ought not to be overlap between the interconnection and that the path connecting between source and terminal must be the shortest “Manhattan Path”. This routing rule can reduce interconnection delay without increasing chip size and it plays an essential role in layout design of high speed IC.

关 键 词：Elmore延迟模型 多端互连线网络 布线时延 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN405.917