一种高速高精度时钟的设计与分析  

Design and Analysis for High-Speed and High-Precision Clock Board

作　　者：阮福明[1] 陈曦[1] 何正淼[1] 安琪[1] 王砚方[1] 

机构地区：[1]中国科技大学近代物理系,合肥230026

出　　处：《数据采集与处理》2005年第3期351-355,共5页Journal of Data Acquisition and Processing

摘　　要：介绍了一种高性能时钟板的设计思想和电路分析。该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟,用于高速高精度背板测试平台。文中给出了实际时钟的性能分析指标,针对影响时钟性能的相关因素,提出高速时钟电路设计的解决方案,并深入探讨了时钟设计中的相关问题。测试结果表明所得时钟信号性能较好。The design and the character analysis in a high performence clock generating system are introduced. The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform. The analysis on actual clock performance is provided, together with the high speed clock circuit design against correlated performance-damaging factors. The rules of the clock design are also discussed. Experimental results show that clock signals have good performances.

关 键 词：频率合成 锁相环 压控晶体振荡器 孔径抖动 

分 类 号：TN92[电子电信—通信与信息系统]