一种基于新型Precharge PFD的CMOS CPPLL设计  

Design of A CMOS CPPLL Based on Novel Precharge PFD

作　　者：胡仕刚[1] 熊元新[1] 司龙[1] 徐征[1] 

机构地区：[1]武汉大学电气工程学院,湖北武汉430072

出　　处：《微电子学与计算机》2005年第9期54-56,60,共4页Microelectronics & Computer

基　　金：国家自然科学基金资助(59977016)

摘　　要：文章描述了一种基于新型无“过充”的边沿触发的鉴频鉴相器的CMOS电荷泵锁相环设计与仿真。电路设计基于UMC2.5V0.25μmCMOS工艺。Spice仿真结果显示,它可以实现快速锁定和较低的抖动性能。The design and simulation of a CMOS CPPLL based on novel edge-triggered precharge PFD are presented in this paper.The PFD is designed to prevent it＇s ouput signal period＇s excess.The circuit design is realized in UMC 2.5V 0.2Sum CMOS technology.Spice simulation shows that a better performance of short lock up time and little jitter.

关 键 词：集成电路 电荷泵 锁相环 鉴频鉴相器 CMOS 

分 类 号：TN911.8[电子电信—通信与信息系统]