逻辑级功耗估计方法的研究  

Power Estimation Techniques at Logic Level

作　　者：刘春燕[1] 原巍[1] 沈绪榜[1] 

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2005年第8期85-89,共5页Microelectronics & Computer

摘　　要：随着芯片规模的增大和速度的不断提高,功耗已经成为深亚微米设计中需要考虑的一个主要因素。在设计中,为了满足功耗需求而又避免进行昂贵地重新设计过程,就需要在设计的不同阶段进行精确而高效的功耗估计。同时,功耗估计对于设计过程中的优化及可靠性设计也是十分重要的。因此,在设计的各个抽象层次出现了很多功耗估计的方法。文章研究了逻辑级功耗估计的方法,重点是近年来提出的几种逻辑级功耗估计的方法,阐述了这些方法的基本原理并比较它们各自的优缺点。With the increase of chip＇s density and operating frequency, power dissipation is recognized as a critical parameter in modem VLSI design field in recent years. We must adopt low power design in all design levels, so power estimation is very important, since it allows checking if the power specifications are met, avoiding the cost of redesign process. And ever increasing power may results in serious reliability problems. Thus, a plenty of power estimators applied at all levels of the design flow have been presented. Here, we will concentrate our attention on the power estimation methods applied at the logic level only. The aim of this article is to describe the main issues of the logic level power estimation, and to present the basic concepts and principles of the most representative published methods.

关 键 词：功耗估计 开关率 基于仿真的功耗估计方法 概率功耗估计方法 

分 类 号：TN4[电子电信—微电子学与固体电子学]