深亚微米CMOS模拟单元电路综合系统  

Synthesis System of Deep-Sub-Micron Cell-Level CMOS Analog Circuit

作　　者：易婷[1] 洪志良[1] 

机构地区：[1]复旦大学微电子学系专用集成电路与系统国家重点实验室,上海200433

出　　处：《计算机辅助设计与图形学学报》2005年第9期2046-2052,共7页Journal of Computer-Aided Design & Computer Graphics

摘　　要：介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统.通过较准确地计算电路的直流工作点和MOS管的小信号参数,以及由电路拓扑结构自动生成电路性能公式对已有的基于公式的方法进行了改进;同时考虑了电路的可制造性问题,使得综合出的电路在工艺波动和工作条件变化时仍能满足性能要求.大量的实验结果表明:与基于模拟器的方法相比,采用该系统可以快速综合出可制造的深亚微米CMOS模拟单元电路.A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper. In the system, the operating point of the circuit and the small signal parameters of MOS transistor are calculated more accurately, and the circuit performance equations are generated from its topology automatically in order to improve the equation-based method. At the same time, manufacturability is taken into account to make the synthesized circuit still meet specifications when parametric fluctuations in the manufacturing process and the variance in their operating conditions occur. It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.

关 键 词：模拟电路综合 优化 集成电路CAD 

分 类 号：TN402[电子电信—微电子学与固体电子学]